An NROM device is a nonvolatile read-only memory electronic memory device which stores charges in a dielectric layer and is well-known in the art. Referring to FIG. 12, there is shown a cross-sectional view of an NROM device 10 of the prior art. In the NROM device 10 of the prior art, the device 10 is made from a silicon substrate 12 with a first conductivity type and a first region 14 and second region 16, spaced apart from one another, which are of a second conductivity type opposite the first conductivity type of the silicon substrate 12. Separating the first region 14 from the second region 16 is a channel region 18. A first insulating layer 20 such as silicon oxide or silicon dioxide is over the channel region 18. A dielectric 22, such as silicon nitride, is positioned “over” the silicon dioxide layer 20. A second insulating layer 24 such as another layer of silicon dioxide 24 is positioned over the dielectric 22. Collectively the first insulating layer 20, the dielectric layer 22 and the second dielectric layer 24 are also known as an ONO layer 20-24. Finally, a polysilicon gate 26 is positioned adjacent to the second layer silicon dioxide 24. Thus, the dielectric 22 is spaced apart and is insulated from the channel region 18 via the first insulating layer 20. The polysilicon gate 26 is insulated and separated from the dielectric 24 by the second insulating layer of silicon dioxide 24. In summary, the polysilicon gate 26 is spaced apart and separated from the channel region 18 by the ONO layer 20-24.
The NROM device 10 is a double density, nonvolatile storage cell, capable of storing 2 bits in a cell. The polysilicon layer 26 serves as the gate and controls the flow of current between the first region 14 and the second regions 16 through the channel region 18. To program one of the bits, the polysilicon gate 26 is raised to a high positive voltage. The first region 14 is held at or near ground and the second region 16 is raised to a high positive voltage. Electrons from the first region 14 accelerate into the channel 18 towards the second channel 16 and through hot channel electron injection mechanism are injected through the first oxide layer 20 and are trapped in the dielectric 22 near the region 30 of the dielectric layer 22. Since the dielectric layer 22, comprising of silicon nitrite is a nonconductive material, the charges are trapped in the region 30.
To program the other bit of the cell 10, the polysilicon layer 26 is raised to a high positive voltage. The second region 16 is held at or near ground and the first region 14 is raised to a high positive voltage. Electrons from the second region 16 accelerate in the channel towards the first region 14 and through hot channel electron injection mechanism are injected through the first silicon dioxide layer 20 and are trapped in the region 28 of the silicon nitride layer 24. Again, since the silicon nitride layer 24 is nonconductive, the charges are trapped in the region 28.
To read one of the bits, the first region 14 is held near ground. A positive bias voltage is applied to the polysilicon layer 26. The voltage applied as such that if the region 28 does not contain trapped charges or is not programmed, it will cause the channel region 18 underneath it to be conductive. However, if the region 28 has trapped charges or is programmed, there will not be a channel to conduct. A positive voltage is also applied to the second region 16. The voltage applied to the second region 16 is such that it causes a depletion region of the second region 16 to expand and encroach the channel region 18 so that it is beyond the region 30. Thus, the state of whether region 30 is programmed or not is irrelevant. Therefore, under that condition, the state of conduction of the channel between the first region 14 and the second region 14 is dependent solely on the state of charge stored or trapped in the region 28.
To read the other bit, the voltages applied are simply reversed. Thus, the second region 16 is held near ground. A positive bias voltage is applied to the polysilicon layer 26. The voltage applied is such that if region 30 is not programmed, it will cause the channel region 18 underneath it to be conductive. However, if region 30 is programmed, there will not be a channel to conduct. A positive voltage is also applied to the first region 14. The voltage applied to first region 14 is such that it causes the depletion region of the first region 14 to expand and encroach into the channel region 18 so that the state of charge stored or trapped in region 28 is irrelevant.
To erase, the substrate 12, the first region 14, and the second region 16, may be connected to a high positive voltage thereby causing Fowler/Nordheim tunneling of electrons from the trapped regions 28 and 30 to tunnel into the substrate 12.
The problem with the NROM cell 10 of the prior art is that the channel 18 is on the planar surface of the silicon substrate 12. The channel region 18 lies in a plane between the first region 14 and the second region 16. Thus, it requires the channel region 18 to be sufficiently large so that the two trapped regions 28 and 30 may be sufficiently separated. This becomes a problem as a cell 10 is scaled to a smaller size. In addition, the thickness of the ONO layers 22-26 cannot be scaled.